Field of the Invention
The present invention relates to high density memory devices, and particularly to memory devices in which multiple planes of memory cells are arranged to provide a three-dimensional 3D array.
Description of Related Art
3D memory devices have been developed in a variety of configurations that include vertical gate structures and vertical channel structures. In vertical gate structures, memory cells including charge storage structures are disposed at interface regions between horizontal planes of active strips including channels for the memory cells, and vertical conductive strips arranged as word lines, string select lines, and ground select lines. In vertical channel structures, memory cells including charge storage structures are disposed at interface regions between horizontal planes of conductive strips arranged as word lines, string select lines, and ground select lines, and vertical active strips including channels for the memory cells. Stacks of active strips in the vertical gate structures are separated by insulating material in a Z-direction, and so are stacks of conductive strips in the vertical channel structures. Thicker insulating material can reduce channel-to-channel interference in the Z-direction between active strips in the vertical gate structures, or reduce gate-to-gate interference in the Z-direction between conductive strips in the vertical channel structures. However, thicker insulating material can also increase the height of the stacks, result in higher aspect ratio of a height over a width of vias or openings in the stacks, and thus cause process issues such as bending.
It is desirable to provide a structure for three-dimensional integrated circuit memory that can reduce the height of the stacks without degrading the device performance, or reduce the Z-direction interference without increasing the height of the stacks.